2019
Sapounaki, Maria; Kakarountas, Athanasios
A High-Performance Neuron for Artificial Neural Network based on Izhikevich model Proceedings Article
In: 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 29–34, IEEE 2019.
@inproceedings{sapounaki2019high,
title = {A High-Performance Neuron for Artificial Neural Network based on Izhikevich model},
author = {Maria Sapounaki and Athanasios Kakarountas},
year = {2019},
date = {2019-01-01},
booktitle = {2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)},
pages = {29--34},
organization = {IEEE},
keywords = {Digital Circuits, FPGA, Hardware Accelerator},
pubstate = {published},
tppubtype = {inproceedings}
}
2017
Chioktour, Vasileios; Spathoulas, Georgios; Kakarountas, Athanasios
Systolic Binary Counter using a Cellular Automaton-based Prescaler Proceedings Article
In: Proceedings of the 21st Pan-Hellenic Conference on Informatics, pp. 1–4, 2017.
@inproceedings{chioktour2017systolicb,
title = {Systolic Binary Counter using a Cellular Automaton-based Prescaler},
author = {Vasileios Chioktour and Georgios Spathoulas and Athanasios Kakarountas},
year = {2017},
date = {2017-01-01},
booktitle = {Proceedings of the 21st Pan-Hellenic Conference on Informatics},
pages = {1--4},
keywords = {Digital Circuits, FPGA, Hardware Accelerator},
pubstate = {published},
tppubtype = {inproceedings}
}
2010
Arvaniti, E; Mavridis, I; Kakarountas, A
Exploration of 2D Cellular Automata as Binary Sequence Generators Proceedings Article
In: 2010 IEEE Computer Society Annual Symposium on VLSI, pp. 41-45, 2010.
@inproceedings{5572756,
title = {Exploration of 2D Cellular Automata as Binary Sequence Generators},
author = {E Arvaniti and I Mavridis and A Kakarountas},
doi = {10.1109/ISVLSI.2010.34},
year = {2010},
date = {2010-01-01},
booktitle = {2010 IEEE Computer Society Annual Symposium on VLSI},
pages = {41-45},
keywords = {Digital Circuits},
pubstate = {published},
tppubtype = {inproceedings}
}
2006
Aisopos, F; Aisopos, K; Schinianakis, D; Michail, H; Kakarountas, A P
A novel high-throughput implementation of a partially unrolled SHA-512 Proceedings Article
In: MELECON 2006 - 2006 IEEE Mediterranean Electrotechnical Conference, pp. 61-65, 2006.
@inproceedings{1653036,
title = {A novel high-throughput implementation of a partially unrolled SHA-512},
author = {F Aisopos and K Aisopos and D Schinianakis and H Michail and A P Kakarountas},
doi = {10.1109/MELCON.2006.1653036},
year = {2006},
date = {2006-01-01},
booktitle = {MELECON 2006 - 2006 IEEE Mediterranean Electrotechnical Conference},
pages = {61-65},
keywords = {Data, Digital Circuits, Hardware Accelerator},
pubstate = {published},
tppubtype = {inproceedings}
}
2005
Kakarountas, A P; Theodoridis, G; Laopoulos, T; Goutis, C E
High-Speed FPGA Implementation of the SHA-1 Hash Function Proceedings Article
In: 2005 IEEE Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, pp. 211-215, 2005.
@inproceedings{4062123,
title = {High-Speed FPGA Implementation of the SHA-1 Hash Function},
author = {A P Kakarountas and G Theodoridis and T Laopoulos and C E Goutis},
doi = {10.1109/IDAACS.2005.282972},
year = {2005},
date = {2005-01-01},
booktitle = {2005 IEEE Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications},
pages = {211-215},
keywords = {Data, Digital Circuits, Hardware Accelerator},
pubstate = {published},
tppubtype = {inproceedings}
}
