2020
Kokkinos, Vasileios; Kakarountas, Athanasios
Design of Reconfigurable Fault-Tolerant Datapaths Proceedings Article
In: 2020 5th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM), pp. 1–6, IEEE 2020.
@inproceedings{kokkinos2020design,
title = {Design of Reconfigurable Fault-Tolerant Datapaths},
author = {Vasileios Kokkinos and Athanasios Kakarountas},
year = {2020},
date = {2020-01-01},
booktitle = {2020 5th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)},
pages = {1--6},
organization = {IEEE},
keywords = {Computer Architecture, Systems},
pubstate = {published},
tppubtype = {inproceedings}
}
2015
Kotsidou, Despoina; Angelis, Constantinos; Dragoumanos, Stamatis; Kakarountas, Athanasios
Computer Assisted Gesture Recognition for the Greek Sign Language / Fingerspelling Proceedings Article
In: Proceedings of the 19th Panhellenic Conference on Informatics, pp. 241–242, Association for Computing Machinery, Athens, Greece, 2015, ISBN: 9781450335515.
@inproceedings{10.1145/2801948.2802034,
title = {Computer Assisted Gesture Recognition for the Greek Sign Language / Fingerspelling},
author = {Despoina Kotsidou and Constantinos Angelis and Stamatis Dragoumanos and Athanasios Kakarountas},
url = {https://doi.org/10.1145/2801948.2802034},
doi = {10.1145/2801948.2802034},
isbn = {9781450335515},
year = {2015},
date = {2015-01-01},
booktitle = {Proceedings of the 19th Panhellenic Conference on Informatics},
pages = {241–242},
publisher = {Association for Computing Machinery},
address = {Athens, Greece},
series = {PCI '15},
abstract = {A significant percentage of the population is suffering from deafness, making simple day-to-day activities hard to complete. Although deaf people have developed a special sign language to communicate, it is a fact that only they and their relatives and friends are capable to use it. This limits significantly communication with other people, and as a consequence, it also limits opportunities. In this paper, the first results of a work-in-progress are presented, that focuses in creating a computer assisted recognition system of the Greek Sign Language. This is the first work of this kind to the best of the knowledge of the authors.},
keywords = {Active Assisted Living, Embedded Systems, Systems},
pubstate = {published},
tppubtype = {inproceedings}
}
A significant percentage of the population is suffering from deafness, making simple day-to-day activities hard to complete. Although deaf people have developed a special sign language to communicate, it is a fact that only they and their relatives and friends are capable to use it. This limits significantly communication with other people, and as a consequence, it also limits opportunities. In this paper, the first results of a work-in-progress are presented, that focuses in creating a computer assisted recognition system of the Greek Sign Language. This is the first work of this kind to the best of the knowledge of the authors.
2014
Kakarountas, A
Disappearing computing for elderly assisted living Proceedings Article
In: 2014 4th International Conference on Wireless Mobile Communication and Healthcare - Transforming Healthcare Through Innovations in Mobile and Wireless Technologies (MOBIHEALTH), pp. 36-38, 2014.
@inproceedings{7015903,
title = {Disappearing computing for elderly assisted living},
author = {A Kakarountas},
doi = {10.1109/MOBIHEALTH.2014.7015903},
year = {2014},
date = {2014-01-01},
booktitle = {2014 4th International Conference on Wireless Mobile Communication and Healthcare - Transforming Healthcare Through Innovations in Mobile and Wireless Technologies (MOBIHEALTH)},
pages = {36-38},
keywords = {Active Assisted Living, Embedded Systems, Health, Smart Home, Systems},
pubstate = {published},
tppubtype = {inproceedings}
}
2010
Soudris, Dimitrios; Piguet, Christian; Goutis, Costas
Designing CMOS circuits for low power Book
Springer Publishing Company, Incorporated, 2010.
@book{soudris2010designing,
title = {Designing CMOS circuits for low power},
author = {Dimitrios Soudris and Christian Piguet and Costas Goutis},
year = {2010},
date = {2010-01-01},
publisher = {Springer Publishing Company, Incorporated},
keywords = {Circuits, Low Powe, Systems},
pubstate = {published},
tppubtype = {book}
}
2009
Schinianakis, D M; Fournaris, A P; Michail, H E; Kakarountas, A P; Stouraitis, T
An RNS Implementation of an $F_p$ Elliptic Curve Point Multiplier Journal Article
In: IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 6, pp. 1202-1213, 2009.
@article{4663678,
title = {An RNS Implementation of an $F_p$ Elliptic Curve Point Multiplier},
author = {D M Schinianakis and A P Fournaris and H E Michail and A P Kakarountas and T Stouraitis},
doi = {10.1109/TCSI.2008.2008507},
year = {2009},
date = {2009-01-01},
journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
volume = {56},
number = {6},
pages = {1202-1213},
keywords = {Systems},
pubstate = {published},
tppubtype = {article}
}
2006
Galanis, Michalis D; Milidonis, Athanassios; Kakarountas, Athanassios P; Goutis, Costas E
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems Journal Article
In: Microelectronics Journal, vol. 37, no. 6, pp. 554-564, 2006, ISSN: 0026-2692.
@article{GALANIS2006554,
title = {A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems},
author = {Michalis D Galanis and Athanassios Milidonis and Athanassios P Kakarountas and Costas E Goutis},
url = {https://www.sciencedirect.com/science/article/pii/S0026269205003538},
doi = {https://doi.org/10.1016/j.mejo.2005.09.032},
issn = {0026-2692},
year = {2006},
date = {2006-01-01},
journal = {Microelectronics Journal},
volume = {37},
number = {6},
pages = {554-564},
abstract = {In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts of applications on coarse-grain reconfigurable hardware. The reconfigurable hardware blocks are embedded in a heterogeneous reconfigurable system architecture. The fine-grain part is implemented by an embedded FPGA unit, while for the coarse-grain reconfigurable hardware our developed high-performance coarse-grain data-path is used. The design flow mainly consists of three steps; the analysis procedure, the mapping onto coarse-grain blocks, and the mapping onto the fine-grain hardware. In this work, the methodology is validated using five real-life applications; an OFDM transmitter, a medical imaging technique, a wavelet-based image compressor, a video compression scheme and a JPEG encoder. The experimental results show that the speedup, relative to an all-FPGA solution, ranges from 1.55 to 4.17 for the considered applications.},
keywords = {FPGA, Hardware, Systems},
pubstate = {published},
tppubtype = {article}
}
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts of applications on coarse-grain reconfigurable hardware. The reconfigurable hardware blocks are embedded in a heterogeneous reconfigurable system architecture. The fine-grain part is implemented by an embedded FPGA unit, while for the coarse-grain reconfigurable hardware our developed high-performance coarse-grain data-path is used. The design flow mainly consists of three steps; the analysis procedure, the mapping onto coarse-grain blocks, and the mapping onto the fine-grain hardware. In this work, the methodology is validated using five real-life applications; an OFDM transmitter, a medical imaging technique, a wavelet-based image compressor, a video compression scheme and a JPEG encoder. The experimental results show that the speedup, relative to an all-FPGA solution, ranges from 1.55 to 4.17 for the considered applications.
