11 entries « ‹ 1 of 2
› » 2010
Soudris, Dimitrios; Piguet, Christian; Goutis, Costas
Designing CMOS circuits for low power Book
Springer Publishing Company, Incorporated, 2010.
@book{soudris2010designing,
title = {Designing CMOS circuits for low power},
author = {Dimitrios Soudris and Christian Piguet and Costas Goutis},
year = {2010},
date = {2010-01-01},
publisher = {Springer Publishing Company, Incorporated},
keywords = {Circuits, Low Powe, Systems},
pubstate = {published},
tppubtype = {book}
}
2008
Kakarountas, Athanasios; Michail, Harris
Performance for Cryptography: hardware and software approach Book Chapter
In: pp. 403-418, 2008, ISBN: 978-1-60456-186-9.
@inbook{inbookb,
title = {Performance for Cryptography: hardware and software approach},
author = {Athanasios Kakarountas and Harris Michail},
isbn = {978-1-60456-186-9},
year = {2008},
date = {2008-01-01},
pages = {403-418},
keywords = {Circuits, Cryptography, Hardware, Hardware Accelerator, security},
pubstate = {published},
tppubtype = {inbook}
}
2004
Karatasos, Dimitris; Kakarountas, Athanasios; Theodoridis, George; Goutis, Costas
A Novel Constant-Time Fault-Secure Binary Counter Proceedings Article
In: Macii, Enrico; Paliouras, Vassilis; Koufopavlou, Odysseas (Ed.): Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, pp. 742–749, Springer Berlin Heidelberg, Berlin, Heidelberg, 2004, ISBN: 978-3-540-30205-6.
@inproceedings{10.1007/978-3-540-30205-6_76,
title = {A Novel Constant-Time Fault-Secure Binary Counter},
author = {Dimitris Karatasos and Athanasios Kakarountas and George Theodoridis and Costas Goutis},
editor = {Enrico Macii and Vassilis Paliouras and Odysseas Koufopavlou},
isbn = {978-3-540-30205-6},
year = {2004},
date = {2004-01-01},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation},
pages = {742--749},
publisher = {Springer Berlin Heidelberg},
address = {Berlin, Heidelberg},
keywords = {Circuits, Safety},
pubstate = {published},
tppubtype = {inproceedings}
}
2003
Kakarountas, A P; Theodoridis, G; Papadomanolakis, K S; Goutis, C
A novel high-speed counter with counting rate independent of the counter's length Proceedings Article
In: 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, pp. 1164-1167 Vol.3, 2003.
@inproceedings{1301719,
title = {A novel high-speed counter with counting rate independent of the counter's length},
author = {A P Kakarountas and G Theodoridis and K S Papadomanolakis and C Goutis},
doi = {10.1109/ICECS.2003.1301719},
year = {2003},
date = {2003-01-01},
booktitle = {10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003},
volume = {3},
pages = {1164-1167 Vol.3},
keywords = {Circuits, Hardware Accelerator, Safety},
pubstate = {published},
tppubtype = {inproceedings}
}
Nikolaidis, S; Karaolis, E; Kakarountas, A; Papadomanolakis, K; Goutis, C E
A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits Journal Article
In: Journal of Circuits, Systems and Computers, vol. 12, no. 01, pp. 75-91, 2003.
@article{doi:10.1142/S0218126603000854,
title = {A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits},
author = {S Nikolaidis and E Karaolis and A Kakarountas and K Papadomanolakis and C E Goutis},
url = {https://doi.org/10.1142/S0218126603000854},
doi = {10.1142/S0218126603000854},
year = {2003},
date = {2003-01-01},
journal = {Journal of Circuits, Systems and Computers},
volume = {12},
number = {01},
pages = {75-91},
abstract = {In this paper, a methodology for the calculation of the undetectable double-faults in self-checking circuits with bit-sliced architecture is introduced. This methodology is based on a systematic exploration of the combinations of nodes where undetectable double-faults can arise. The self-checking n-bit 2-to-1 multiplexer coded by parity is used as a test vehicle for the presentation of the methodology and the number of the undetectable double-faults is given in a parametric way. The proposed methodology can easily be applied to other bit-sliced circuits. Common self-checking circuits are implemented for different coding schemes and are using standard cell technology to verify the proposed methodology. The effectiveness of these implementations in fault detection as well as their requirements in hardware and power are also investigated.},
keywords = {Circuits, Low Power},
pubstate = {published},
tppubtype = {article}
}
In this paper, a methodology for the calculation of the undetectable double-faults in self-checking circuits with bit-sliced architecture is introduced. This methodology is based on a systematic exploration of the combinations of nodes where undetectable double-faults can arise. The self-checking n-bit 2-to-1 multiplexer coded by parity is used as a test vehicle for the presentation of the methodology and the number of the undetectable double-faults is given in a parametric way. The proposed methodology can easily be applied to other bit-sliced circuits. Common self-checking circuits are implemented for different coding schemes and are using standard cell technology to verify the proposed methodology. The effectiveness of these implementations in fault detection as well as their requirements in hardware and power are also investigated.
2002
Papadomanolakis, K S; Kakarountas, Athanasios; Sklavos, Nicolas; Goutis, C E
A Fast Johnson-Mobius Encoding Scheme for Fault Secure Binary Counters Proceedings Article
In: 2002.
@inproceedings{inproceedingsb,
title = {A Fast Johnson-Mobius Encoding Scheme for Fault Secure Binary Counters},
author = {K S Papadomanolakis and Athanasios Kakarountas and Nicolas Sklavos and C E Goutis},
year = {2002},
date = {2002-01-01},
keywords = {Circuits, Safety, VLSI},
pubstate = {published},
tppubtype = {inproceedings}
}
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