2006
Kakarountas, A P; Zervas, N D; Theodoridis, G; Michail, H E; Soudris, D
Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers Journal Article
In: Journal of Low Power Electronics, vol. 2, no. 3, pp. 356–364, 2006, ISSN: 1546-1998.
@article{Kakarountas:2006:1546-1998:356,
title = {Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers},
author = {A P Kakarountas and N D Zervas and G Theodoridis and H E Michail and D Soudris},
url = {https://www.ingentaconnect.com/content/asp/jolpe/2006/00000002/00000003/art00004},
doi = {doi:10.1166/jolpe.2006.083},
issn = {1546-1998},
year = {2006},
date = {2006-01-01},
journal = {Journal of Low Power Electronics},
volume = {2},
number = {3},
pages = {356--364},
keywords = {Low Power},
pubstate = {published},
tppubtype = {article}
}
2004
Kakarountas, Athanasios P; Spiliotopoulos, Vassilis; Nikolaidis, Spiros; Goutis, Costas E
The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems Proceedings Article
In: Macii, Enrico; Paliouras, Vassilis; Koufopavlou, Odysseas (Ed.): Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, pp. 501–509, Springer Berlin Heidelberg, Berlin, Heidelberg, 2004, ISBN: 978-3-540-30205-6.
@inproceedings{10.1007/978-3-540-30205-6_52,
title = {The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems},
author = {Athanasios P Kakarountas and Vassilis Spiliotopoulos and Spiros Nikolaidis and Costas E Goutis},
editor = {Enrico Macii and Vassilis Paliouras and Odysseas Koufopavlou},
isbn = {978-3-540-30205-6},
year = {2004},
date = {2004-01-01},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation},
pages = {501--509},
publisher = {Springer Berlin Heidelberg},
address = {Berlin, Heidelberg},
abstract = {The application of typical low-power techniques on safety-critical systems may result in degradation of crucial safety properties of the system. However, existing techniques to address this impact, considered that low-power mode is applied for short time intervals. Thus, addressing degradation of the safety properties only on checkers was considered sufficient. A novel approach is introduced that considers both requirements for safe operation and low-Low-power dissipation. The benefits of this approach are exhibited and a comparison to alternative approaches is offered.},
keywords = {Low Power},
pubstate = {published},
tppubtype = {inproceedings}
}
The application of typical low-power techniques on safety-critical systems may result in degradation of crucial safety properties of the system. However, existing techniques to address this impact, considered that low-power mode is applied for short time intervals. Thus, addressing degradation of the safety properties only on checkers was considered sufficient. A novel approach is introduced that considers both requirements for safe operation and low-Low-power dissipation. The benefits of this approach are exhibited and a comparison to alternative approaches is offered.
2003
Nikolaidis, S; Karaolis, E; Kakarountas, A; Papadomanolakis, K; Goutis, C E
A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits Journal Article
In: Journal of Circuits, Systems and Computers, vol. 12, no. 01, pp. 75-91, 2003.
@article{doi:10.1142/S0218126603000854,
title = {A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits},
author = {S Nikolaidis and E Karaolis and A Kakarountas and K Papadomanolakis and C E Goutis},
url = {https://doi.org/10.1142/S0218126603000854},
doi = {10.1142/S0218126603000854},
year = {2003},
date = {2003-01-01},
journal = {Journal of Circuits, Systems and Computers},
volume = {12},
number = {01},
pages = {75-91},
abstract = {In this paper, a methodology for the calculation of the undetectable double-faults in self-checking circuits with bit-sliced architecture is introduced. This methodology is based on a systematic exploration of the combinations of nodes where undetectable double-faults can arise. The self-checking n-bit 2-to-1 multiplexer coded by parity is used as a test vehicle for the presentation of the methodology and the number of the undetectable double-faults is given in a parametric way. The proposed methodology can easily be applied to other bit-sliced circuits. Common self-checking circuits are implemented for different coding schemes and are using standard cell technology to verify the proposed methodology. The effectiveness of these implementations in fault detection as well as their requirements in hardware and power are also investigated.},
keywords = {Circuits, Low Power},
pubstate = {published},
tppubtype = {article}
}
In this paper, a methodology for the calculation of the undetectable double-faults in self-checking circuits with bit-sliced architecture is introduced. This methodology is based on a systematic exploration of the combinations of nodes where undetectable double-faults can arise. The self-checking n-bit 2-to-1 multiplexer coded by parity is used as a test vehicle for the presentation of the methodology and the number of the undetectable double-faults is given in a parametric way. The proposed methodology can easily be applied to other bit-sliced circuits. Common self-checking circuits are implemented for different coding schemes and are using standard cell technology to verify the proposed methodology. The effectiveness of these implementations in fault detection as well as their requirements in hardware and power are also investigated.
2002
Kakarountas, AP; Papadomanolakis, KS; Spiliotopoulos, V; Nikolaidis, S; Goutis, CE
Designing a Low-Power Fault-Tolerant Microcontroller for Medicine Infusion Devices Journal Article
In: Proceedings of Design, Automation & Test in Europe (DATE’02), 2002.
@article{kakarountas2002designing,
title = {Designing a Low-Power Fault-Tolerant Microcontroller for Medicine Infusion Devices},
author = {AP Kakarountas and KS Papadomanolakis and V Spiliotopoulos and S Nikolaidis and CE Goutis},
year = {2002},
date = {2002-01-01},
journal = {Proceedings of Design, Automation & Test in Europe (DATE’02)},
keywords = {Hardware Accelerator, Low Power},
pubstate = {published},
tppubtype = {article}
}
2001
Papadomanolakis, K; Kakarountas, A; Kokkinos, V; Sklavos, N; Goutis, C
The Effect of Fault Secureness in Low Power Multiplier Designs Proceedings Article
In: 2001.
@inproceedings{Papadomanolakis2001TheEO,
title = {The Effect of Fault Secureness in Low Power Multiplier Designs},
author = {K Papadomanolakis and A Kakarountas and V Kokkinos and N Sklavos and C Goutis},
year = {2001},
date = {2001-01-01},
keywords = {Circuits, Computer Arcitecture, Low Power, Systems},
pubstate = {published},
tppubtype = {inproceedings}
}
2000
Papndomanolakis, K; Kakarountas, A P; Kokkinos, V; Goutis, C E
Low-Power Design of a Safety Critical Microcontroller Proceedings Article
In: MMN 2000. 1st Conference on Microelectronics, Microsystems and Nanotechnology, 2000.
@inproceedings{957515,
title = {Low-Power Design of a Safety Critical Microcontroller},
author = {K Papndomanolakis and A P Kakarountas and V Kokkinos and C E Goutis},
year = {2000},
date = {2000-01-01},
booktitle = {MMN 2000. 1st Conference on Microelectronics, Microsystems and Nanotechnology},
keywords = {Low Power, Safety},
pubstate = {published},
tppubtype = {inproceedings}
}
